1. Field of the Invention
The present invention relates to a semiconductor device including an MiM (Metal Insulator Metal) capacitor element and a fabrication method thereof. The present invention can be applied to fabrication of a capacitor element using photolithography. In particular, the present invention is suitable for fabrication of an MiM capacitor element in a semiconductor device.
2. Description of the Related Art
Conventionally, an MiM capacitor element is used as a capacitor element formed in a semiconductor device. The MiM capacitor element has a lower electrode formed of metal or alloy (hereinafter, collectively referred to as metal), an upper electrode formed of metal, and an insulation layer formed between the lower and upper electrodes. (See Japanese Patent Laid-Open Publication No. 2003-31665, FIGS. 1 to 3, for example.)
A fabrication method of the MiM capacitor element disclosed in Japanese Patent Laid-Open Publication No. 2003-31665 is now described. First, an insulation layer is formed on a semiconductor substrate. On the insulation layer, a lower electrode layer, a dielectric layer, and an upper electrode layer are formed in that order. Then, a first resist pattern is formed, and thereafter the upper electrode layer is etched using the first resist pattern as a mask so as to form an upper electrode pattern. The first resist pattern is then removed and a second resist pattern is formed to cover the upper electrode pattern. Using the second resist pattern as a mask, the dielectric layer is etched to form a dielectric pattern. Then, the second resist pattern is removed and a third resist pattern is formed to cover the upper electrode pattern and the dielectric pattern. Using the third resist pattern as a mask, the lower electrode layer is etched to form a lower electrode pattern. In this manner, the MiM capacitor element is fabricated.
However, in the conventional fabrication method described above, it is necessary to perform photolithography three times in order to form the MiM capacitor element. Thus, three masks are required and the number of the performed processes is large. This means that a fabrication cost is expensive.
Therefore, another fabrication method is proposed in which an MiM capacitor element is fabricated by performing photolithography twice. Such a conventional fabrication method of a semiconductor device including an MiM capacitor element is described below. FIGS. 1 to 4 are cross-sectional views showing processes of the conventional fabrication method of the semiconductor device in an order in which the processes are performed. As shown in FIGS. 1 to 4, in this semiconductor device, an MiM region 11 in which an MiM capacitor element is to be formed and a wiring region 12 in which a wiring is to be formed are provided.
First, as shown in FIG. 1, an insulation layer 2 is formed on a silicon substrate 1. On the insulation layer 2, an Al layer is deposited to form a lower conductive layer 3a. Then, an SiO or SiON layer is deposited by plasma CVD method (Plasma-enhanced Chemical Vapor Deposition method) on the lower conductive layer 3a to form a capacitor-insulator layer 4d. On the capacitor-insulator layer 4d, a TiN layer is deposited, so that an upper conductive layer 5a is formed. Then, a photoresist layer is formed on the upper conductive layer 5a and is patterned to form a resist pattern 6 in the MiM region 11. Using the resist pattern 6 as a mask, the upper conductive layer 5a and the capacitor-insulator layer 4d are etched to be selectively removed, so that an upper electrode 5 of TiN and a capacitor insulation layer 14 of SiO or SiON are obtained. Then, the resist pattern 6 is removed.
Next, as shown in FIG. 2, another photoresist layer is formed on the lower conductive layer 3a (see FIG. 1) to cover the capacitor insulation layer 14 and the upper electrode 5. Then, the photoresist layer is patterned to form a resist pattern 7 in both the MiM region 11 and the wiring region 12. Using the resist pattern 7 as a mask, the lower conductive layer 3a is etched to be selectively removed, so that a lower electrode 3 of Al is formed in the MiM region 11. At the same time, a lower wiring 13 of Al is formed in the wiring region 12. Then, the resist pattern 7 is removed.
Next, as shown in FIG. 3, an insulation layer 8 is formed on the insulation layer 2 to cover the lower electrode 3, the lower wiring 13, the capacitor insulation layer 14, and the upper electrode 5. The surface of the insulation layer 8 is flattened. Then, a plurality of via holes 9 are formed in the insulation layer 8 to connect with the upper electrode 5, the lower electrode 3, and the lower wiring 13, respectively.
Next, as shown in FIG. 4, upper wirings 10 are formed on the insulation layer 8 in regions containing regions directly above the via holes 9. Thus, the upper wirings 10 are connected to the upper electrode 5, the lower electrode 3, and the lower wiring 13 through the via holes 9. In this manner, a semiconductor device which includes the MiM capacitor element formed by the upper electrode 5, the capacitor insulation layer 14 and the lower electrode 3 is fabricated.
In this semiconductor device, the MiM capacitor element works as a capacitor when a voltage is applied between the upper electrode 5, and the lower electrode 3 via the upper wirings 10 and the via holes 9. According to the aforementioned fabrication method, the MiM capacitor element having a three-layer structure can be formed by performing photolithography twice.
However, the conventional fabrication method described above has the following problem. In the process of the above fabrication method, shown in FIG. 1, the upper conductive layer 5a and the capacitor-insulator layer 4d are etched using the resist pattern 6 as a mask. By this etching, the upper conductive layer 5a and the capacitor-insulator layer 4d are completely removed in a region having no resist pattern 6 formed therein, so that the lower conductive layer 3a is exposed to the etching gas. Thus, part of the material (Al) forming the lower conductive layer 3a leaves the lower conductive layer 3a to the atmosphere and adheres to side faces of the upper electrode 5 and capacitor insulation layer 14 as conductive deposit. The conductive deposit may cause a leak current between the upper electrode 5 and the lower electrode 3 in a resultant MiM capacitor element, thus degrading the performance of the MiM capacitor element.